Existing redundancy schemes may utilize two or more transmitters each configured to transmit the same data. From time to time, it may be necessary to obtain one or more updatable parameters, such as a sampled count or a sampled state, for each of the transmitters. However, sampling the counters and states for each of the transmitters is problematic in terms of synchronization. If each of a respective plurality of transmitters is configured with its own corresponding thread that runs on a processor core that is programmed to control the transmission of data and run a protocol state machine, then a general-purpose central processing unit (CPU) reading of the counters and states on each transmitter may not yield an accurate snapshot of the counters and states. Multiple threads or CPUs do not always obtain the same value when reading a counter or state. This undesired outcome is caused by bus latencies as well as utilization of separate read cycles. Essentially, the CPU must perform a plurality of temporally dislocated read operations. Moreover, if the counter or state is being reset after the read, the period between the read and the write to reset can result in information being lost. If the redundancy scheme is reliant on, or if its implementation is simplified by, obtaining samples for the counts and states unambiguously, then it may be difficult or impossible to achieve deterministic synchronization among the two or more transmitters.
Cache algorithms and features have been proposed to provide deterministic synchronization and coherency in multiple-transmitter systems where temporally dislocated multiple read operations need to be performed. These cache-based approaches focus on addresses and cache line concurrency. However, cache-based approaches are geared toward homogeneous core complexes, and complex hardware is therefore required for coherent sampling and clearing of counters and states in heterogeneous systems. A heterogeneous system may include, for example, a core complex interfacing to offload hardware with embedded proprietary or heterogeneous cores that may not have data cache hardware.
For at least these reasons, therefore, it would be advantageous if new or improved systems and methods for performing unambiguous counter and state sampling in a heterogeneous multi-core or multi-threaded environment could be achieved that address one or more of the previously-discussed limitations or other limitations.